3-45 file number 3181.3 ICL7662 cmos voltage converter the intersil ICL7662 is a monolithic high-voltage cmos power supply circuit which offers unique performance ad- vantages over previously available devices. the ICL7662 performs supply voltage conversion from positive to negative for an input range of +4.5v to +20.0v, resulting in complementary output voltages of -4.5v to -20v. only 2 noncritical external capacitors are needed for the charge pump and charge reservoir functions. the ICL7662 can also function as a voltage doubler, and will generate output voltages up to +38.6v with a +20v input. contained on chip are a series dc power supply regulator, rc oscillator, voltage level translator, four output power mos switches. a unique logic element senses the most negative voltage in the device and ensures that the output n-channel switch source-substrate junctions are not forward biased. this assures latchup free operation. the oscillator, when unloaded, oscillates at a nominal frequency of 10khz for an input supply voltage of 15.0v. this frequency can be lowered by the addition of an external capacitor to the osc terminal, or the oscillator may be overdriven by an external clock. the lv terminal may be tied to ground to bypass the internal series regulator and improve low voltage (lv) operation. at medium to high voltages (+10v to +20v), the lv pin is left ?oating to prevent device latchup. features ? no external diode needed over entire temperature range ? pin compatible with icl7660 ? simple conversion of +15v supply to -15v supply ? simple voltage multiplication (v out = (-)nv in ) ? 99.9% typical open circuit voltage conversion ef?ciency ? 96% typical power ef?ciency ? wide operating voltage range 4.5v to 20.0v ? easy to use - requires only 2 external non-critical passive components applications ? on board negative supply for dynamic rams ? localized m processor (8080 type) negative supplies ? inexpensive negative supplies ? data acquisition systems ? up to -20v for op amps pinouts ICL7662cbd-0 (soic) top view ICL7662cbd and ibd (soic) top view ICL7662 (can) top view ICL7662 (pdip) top view test nc cap+ nc gnd nc cap- v+ osc nc lv nc nc v out 1 2 3 4 5 6 7 14 13 12 11 10 9 8 nc test nc cap+ gnd nc nc v+ nc osc lv nc v out cap- 1 2 3 4 5 6 7 14 13 12 11 10 9 8 v+ lv cap+ test gnd osc v out 2 4 6 1 3 7 5 8 test cap+ gnd cap- 1 2 3 4 8 7 6 5 v+ osc lv v out data sheet april 1999 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. http://www.intersil.com or 407-727-9207 | copyright ? intersil corporation 1999
3-46 functional block diagram ordering information part number temp. range ( o c) package pkg. no. ICL7662ctv 0 to 70 8 pin metal can t8.c ICL7662cpa 0 to 70 8 ld pdip e8.3 ICL7662cbd-0 0 to 70 14 ld soic (n) m14.15 ICL7662cbd 0 to 70 14 ld soic (n) m14.15 ICL7662itv -40 to 85 8 pin metal can t8.c ICL7662ipa -40 to 85 8 ld pdip e8.3 ICL7662ibd -40 to 85 14 ld soic (n) m14.15 ICL7662mtv (note 1) -55 to 125 8 pin metal can t8.c note: 1. add /883 to part number if /883b processing is required. rc oscillator ? 2 voltage regulator logic network osc lv v+ cap+ cap- v out voltage level translator test p n ICL7662
3-47 absolute maximum ratings thermal information supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22v oscillator input voltage . . . . . . . . -0.3v to (v+ +0.3v) for v+ < 10v . . . . . . . . . . . . . . . . . (note 2) (v+ -10v) to (v+ +0.3v) for v+ > 10v current into lv (note 2) . . . . . . . . . . . . . . . . . . . . 20 m a for v+ > 10v output short duration . . . . . . . . . . . . . . . . . . . . . . . . . . .continuous thermal resistance (typical, note 3) q ja ( o c/w) q jc ( o c/w) pdip package . . . . . . . . . . . . . . . . . . . 150 n/a plastic soic package . . . . . . . . . . . . . 120 n/a metal can. . . . . . . . . . . . . . . . . . . . . . . 156 68 maximum lead temperature (soldering, 10s). . . . . . . . . . . . .300 o c (soic - lead tips only) caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio nofthe device at these or any other conditions above those indicated in the operational sections of this speci?cation is not implied. notes: 2. connecting any terminal to voltages greater than v+ or less than gnd may cause destructive latchup. it is recommended that no inputs from sources operating from external supplies be applied prior to power up of icl7660s. 3. q ja is measured with the component mounted on an evaluation pc board in free air. electrical speci?cations v+ = 15v, t a = 25 o c, c osc = 0, unless otherwise speci?ed. refer to figure 14. parameter symbol test conditions min typ max units supply voltage range - lo v+l r l = 10k w , lv = gnd min < t a < max 4.5 - 11 v supply voltage range - hi v+h r l = 10k w , lv = open min < t a < max 9 - 20 v supply current i+ r l = , lv = open t a = 25 o c - 0.25 0.60 ma 0 o c < t a < 70 o c -40 o c < t a < 85 o c - 0.30 0.85 ma -55 o c < t a < 125 o c - 0.40 1.0 ma output source resistance r o i o = 20ma, lv = open t a = 25 o c - 60 100 w 0 o c < t a < 70 o c -40 o c < t a < 85 o c - 70 120 w -55 o c < t a < 125 o c - 90 150 w supply current i+ v+ = 5v, r l = , lv = gnd t a = 25 o c - 20 150 m a 0 o c < t a < 70 o c -40 o c < t a < 85 o c - 25 200 m a -55 o c < t a < 125 o c - 30 250 m a output source resistance r o v+ = 5v, i o = 3ma, lv = gnd t a = 25 o c - 125 200 w 0 o c < t a < 70 o c -40 o c < t a < 85 o c - 150 250 w -55 o c < t a < 125 o c - 200 350 w oscillator frequency fosc - 10 - khz power efficiency p eff r l = 2k w t a = 25 o c9396-% min < t a < max 90 95 - % voltage conversion efficiency voef r l = min < t a < max 97 99.9 - % oscillator sink or source current i osc v+ = 5v (v osc = 0v to +5v) - 0.5 - m a v+ = 15v (v osc = +5v to +15v) - 4.0 - m a note: 4. pin 1 is a test pin and is not connected in normal use. when the test pin is connected to v+, an internal transmission gate disconnects any external parasitic capacitance from the oscillator which would otherwise reduce the oscillator frequency from its nominal value . ICL7662
3-48 typical performance curves (see figure 14, test circuit) figure 1. output source resistance as a function of supply voltage figure 2. output source resistance as a function of supply voltage figure 3. output source resistance as a function of temperature figure 4. power conversion efficiency and output source resistance as a function of oscillator frequency figure 5. osclllator frequency vs supply voltage figure 6. frequency of oscillation as a function of external oscillator capacitance note: all typical values have been characterized but are not tested. output resistance ( w ) 190 170 150 130 110 90 70 50 30 0 2 4 6 8 10 12 14 16 18 20 v+ (v) lv = gnd lv = open i l = 20ma t a = 25 o c c osc = 0pf v+ (v) 0 2 4 6 8 10 12 14 16 18 20 190 170 150 130 110 90 70 50 30 output resistance ( w ) i l = 3ma t a = 25 o c c osc = 0pf lv = gnd lv = open temperature ( o c) -55 -20 0 25 70 125 180 170 160 150 140 130 120 110 100 90 80 70 60 50 output resistance ( w ) v+ = 5v i l = 3ma v+ = 15v i l = 20ma power conversion efficiency (%) output resistance ( w ) f osc (hz) 100 95 90 85 80 75 70 65 350 300 250 200 150 100 50 100 1k 10k 100k v+ = 5v i l = 3ma t a = 25 o c p eff r o 11 10 9 8 7 6 5 4 3 2 oscillator frequency (khz) 02468101214161820 supply voltage (v) lv = gnd lv = open r l = t a = 25 o c c osc = 0pf c osc (pf) oscillator frequency (hz) 10k 1k 100 10 1 10 100 1000 10k v+ = 15v t a = 25 o c r l = ICL7662
3-49 figure 7. unloaded osclllator frequency as a function of temperature figure 8. output voltage as a function of load current figure 9. output voltage as a function of load current figure 10. supply current and power conversion efficiency as a function of load figure 11. supply current and power conversion efficiency as a function of load current figure 12. frequency of oscillation as a function of supply voltage typical performance curves (see figure 14, test circuit) (continued) temperature ( o c) 15k 14k 13k 12k 11k 10k 9k 8k 7k 6k 5k oscillator frequency (hz) -55 -20 0 25 70 125 v+ = 15v c osc = 0pf output voltage v o (v) -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 10 20 30 40 50 60 70 80 90 100 load current i l (ma) slope = 65 w v+ = 15v t a = 25 o c lv = open 2 1 0 -1 -2 -3 -4 -5 02468101214161820 load current i l (ma) output voltage vo (v) v+ = 5v t a = 25 o c lv = gnd slope = 14 w 100 95 90 85 80 75 70 65 power conversion efficiency (%) 40 32 24 16 8 supply current i+ (ma) 0 2 4 6 8 101214161820 load current i l (ma) v+ = 5v t a = 25 o c pbff i+ power conversion efficiency (%) 100 95 90 85 80 75 70 65 0102030405060708090100 200 160 120 80 40 supply current i+ (ma) v+ = 15v t a = 25 o c pbff i+ load current i l (ma) 11 10 9 8 7 6 5 4 3 2 oscillator frequency (khz) 0 2 4 6 8101214161820 supply voltage (v) lv = gnd lv = open r l = t a = 25 o c c osc = 0pf ICL7662
3-50 circuit description the ICL7662 contains all the necessary circuitry to complete a negative voltage converter, with the exception of 2 external capacitors which may be inexpensive 10 m f polarized electrolytic capacitors. the mode of operation of the device may be best understood by considering figure 15, which shows an idealized negative voltage converter. capacitor c 1 is charged to a voltage, v+, for the half cycle when switches s 1 and s 3 are closed. (note: switches s 2 and s 4 are open during this half cycle.) during the second half cycle of operation, switches s 2 and s 4 are closed, with s 1 and s 3 open, thereby shifting capacitor c 1 negatively by v+ volts. charge is then transferred from c 1 to c 2 such that the voltage on c 2 is exactly v+, assuming ideal switches and no load on c 2 . the lcl7662 approaches this ideal situation more closely than existing non-mechanical circuits. in the lcl7662, the 4 switches of figure 15 are mos power switches; s 1 is a p-channel device and s 2 , s 3 and s 4 are n-channel devices. the main dif?culty with this approach is that in integrating the switches, the substrates of s 3 and s 4 must always remain reverse biased with respect to their sources, but not so much as to degrade their on resistances. in addition, at circuit startup, and under output short circuit conditions (v out = v+), the output voltage must be sensed and the substrate bias adjusted accordingly. failure to accomplish this would result in high power losses and probable device latchup. this problem is eliminated in the ICL7662 by a logic network which senses the output voltage (v out ) together with the level translators, and switches the substrates of s 3 and s 4 to the correct level to maintain necessary reverse bias. the voltage regulator portion of the ICL7662 is an integral part of the anti-latchup circuitry, however its inherent voltage drop can degrade operation at low voltages. therefore, to improve low voltage operation the lv pin should be connected to ground, disabling the regulator. for supply voltages greater than 10v the lv terminal must be left open to insure latchup proof operation, and prevent device damage. figure 13. supply current as a function of oscillator frequency note: 5. these curves include in the supply current that current fed directly into the load r l from the v+ (see figure 14). thus, approximately half the supply current goes directly to the positive side of the load, and the other half, through the ICL7662, to the negative side of the load. ideally, v out ~ 2v in , i s ~ 2i l , so v in x i s ~ v out x i l . typical performance curves (see figure 14, test circuit) (continued) 150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 supply current i+ ( m a) 10 100 1k 10k oscillator frequency (hz) 1 2 3 4 8 7 6 5 + - c 1 (+5v) i l r l -v out c 2 10 m f ICL7662 c osc + - i s v+ (note) note: for large value of c osc (> 1000pf) the values of c 1 and c 2 should be increased to 100 m f. figure 14. ICL7662 test circuit ICL7662
3-51 theoretical power ef?ciency considerations in theory a voltage multiplier can approach 100% ef?ciency if certain conditions are met: 1. the drive circuitry consumes minimal power. 2. the output switches have extremely low on resistance and virtually no offset. 3. the impedances of the pump and reservoir capacitors are negligible at the pump frequency. the ICL7662 approaches these conditions for negative voltage multiplication if large values of c 1 and c 2 are used. energy is lost only in the transfer of charge between capacitors if a change in voltage occurs. the energy lost is de?ned by: e = 1/2c 1 (v 1 2 - v 2 2 ) where v 1 and v 2 are the voltages on c 1 during the pump and transfer cycles. if the impedances of c 1 and c 2 are relatively high at the pump frequency (refer to figure 15) compared to the value of r l , there will be a substantial difference in the voltages v 1 and v 2 . therefore it is not only desirable to make c 2 as large as possible to eliminate output voltage ripple, but also to employ a correspondingly large value for c 1 in order to achieve maximum ef?ciency of operation. dos and donts 1. do not exceed maximum supply voltages. 2. do not connect lv terminal to ground for supply voltag- es greater than 10v. 3. when using polarized capacitors, the + terminal of c 1 must be connected to pin 2 of the ICL7662 and the + ter- minal of c 2 must be connected to ground. 4. if the voltage supply driving the 7662 has a large source impedance (25 w -30 w ), then a 2.2 m f capacitor from pin 8 to ground may be required to limit rate of rise of input voltage to less than 2v/ m s. 5. user should insure that the output (pin 5) does not go more positive than gnd (pin 3). device latch up will occur under these conditions. a 1n914 or similar diode placed in parallel with c 2 will prevent the device from latching up under these conditions. (anode pin 5, cathode pin 3). typical applications simple negative voltage converter the majority of applications will undoubtedly utilize the ICL7662 for generation of negative supply voltages. figure 16 shows typical connections to provide a negative supply where a positive supply of +4.5v to 20.0v is available. keep in mind that pin 6 (lv) is tied to the supply negative (gnd) for supply voltages below 10v. the output characteristics of the circuit in figure 16a can be approximated by an ideal voltage source in series with a resistance as shown in figure 16b. the voltage source has a value of -(v+). the output impedance (r o ) is a function of the on resistance of the internal mos switches (shown in figure 2), the switching frequency, the value of c 1 and c 2 , and the esr (equivalent series resistance) of c 1 and c 2 . a good ?rst order approximation for r o is: combining the four r swx terms as r sw , we see that r sw , the total switch resistance, is a function of supply voltage and temperature (see the output source resistance graphs), typically 24 w at +25 o c and 15v, and 53 w at +25 o c and 5v. careful selection of c 1 and c 2 will reduce the remaining terms, minimizing the output impedance. high value capacitors will reduce the 1/(f pump x c 1 ) component, and low fsr capacitors will lower the esr term. increasing the oscillator frequency will reduce the 1/(f pump xc 1 ) term, but may have the side effect of a net increase in output impedance when c 1 > 10 m f and there is no longer enough time to fully charge the capacitors every cycle. in a typical application where f osc = 10khz and c = c 1 = c 2 = 10 m f: since the esrs of the capacitors are re?ected in the output impedance multiplied by a factor of 5, a high value could potentially swamp out a low 1/(f pump x c 1 ) term, rendering an increase in switching frequency or ?lter capacitance ineffective. typical electrolytic capacitors may have esrs as high as 10 w . v out = -v in c 2 v in c 1 s 3 s 4 s 1 s 2 8 2 4 5 3 3 7 figure 15. idealized negative converter r o @ 2(r sw1 + r sw3 + esrc 1 ) + 2(r sw2 + r sw4 + esrc 1 ) + 1 + esrc 2 f pump x c 1 (f pump = f osc , r swx = mosfet switch resistance) 2 r o @ 2 x r sw + 1 + 4 x esrc 1 + esrc 2 w f pump x c 1 r o @ 2 x 23 + 1 + 4 esrc 1 + esrc 2 (5 x 10 3 x 10 x 10 -6 ) r o @ 46 + 20 + 5 x esr c w ICL7662
3-52 output ripple esr also affects the ripple voltage seen at the output. the total ripple is determined by 2v, a and b, as shown in figure 16. segment a is the voltage drop across the esr of c 2 at the instant it goes from being charged by c 1 (current ?owing into c 2 ) to being discharged through the load (current ?owing out of c 2 ). the magnitude of this current change is 2 xi out , hence the total drop is 2 x i out x esrc 2 v. segment b is the voltage change across c 2 during time t 2 , the half of the cycle when c 2 supplies current the load. the drop at b is i out xt 2 /c 2 v. the peak-to-peak ripple voltage is the sum of these voltage drops: again, a low esr capacitor will result in a higher performance output. paralleling devices any number of ICL7662 voltage converters may be paralleled (figure 18) to reduce output resistance. the reservoir capacitor, c 2 , serves all devices while each device requires its own pump capacitor, c 1 . the resultant output resistance would be approximately: cascading devices the ICL7662 may be cascaded as shown in figure 19 to produce larger negative multiplication of the initial supply voltage. however, due to the ?nite ef?ciency of each device, the practical limit is 10 devices for light loads. the output voltage is de?ned by: v out = -n(v in ), where n is an integer representing the number of devices cascaded. the resulting output resistance would be approximately the weighted sum of the individual ICL7662 r out values. 1 2 3 4 8 7 6 5 + - 10 m f 10 m f ICL7662 v out = -v+ v+ + - r o v out v+ + - 16a. 16b. c 1 c 2 figure 16. simple negative converter and its output equivalent v ripple 1 2f pump c 2 ----------------------------------------- 2 esrc 2 i out + ? ?? @ r out = r out (of ICL7662) n (number of devices) figure 17. output ripple figure 18. paralleling devices a t 2 t 1 b 0 -(v+) v 1 2 3 4 8 7 6 5 ICL7662 v+ c 1 1 1 2 3 4 8 7 6 5 ICL7662 c 1 n r l c 2 + - ICL7662
3-53 changing the ICL7662 oscillator frequency it may be desirable in some applications, due to noise or other considerations, to increase the oscillator frequency. this is achieved by overdriving the oscillator from an external clock, as shown in figure 20. in order to prevent possible device latchup, a 1k w resistor must be used in series with the clock output. in the situation where the designer has generated the external clock frequency using ttl logic, the addition of a 10k w pullup resistor to v+ supply is required. note that the pump frequency with external clocking, as with internal clocking, will be 1/2 of the clock frequency. output transitions occur on the positive- going edge of the clock. it is also possible to increase the conversion efficiency of the ICL7662 at low load levels by lowering the oscillator frequency. this reduces the switching losses, and is achieved by connecting an additional capacitor, cosc, as shown in figure 21. however, lowering the oscillator frequency will cause an undesirable increase in the impedance of the pump (c 1 ) and reservoir (c 2 ) capacitors; this is overcome by increasing the values of c 1 and c 2 by the same factor that the frequency has been reduced. for example, the addition of a 100pf capacitor between pin 7 (osc) and v+ will lower the oscillator frequency to 1khz from its nominal frequency of 10khz (a multiple of 10), and thereby necessitate a corresponding increase in the value of c 1 and c 2 (from 10mf to 100mf). positive voltage doubling the ICL7662 may be employed to achieve positive voltage doubling using the circuit shown in figure 22. in this application, the pump inverter switches of the ICL7662 are used to charge c 1 to a voltage level of v+ -v f (where v+ is the supply voltage and v f is the forward voltage drop of diode d 1 ). on the transfer cycle, the voltage on c 1 plus the supply voltage (v+) is applied through diode c 2 to capacitor c 2 . the voltage thus created on c 2 becomes (2v+) (2v f )or twice the supply voltage minus the combined forward voltage drops of diodes d 1 and d 2 . the source impedance of the output (v out ) will depend on the output current, but for v+ = 15v and an output current of 10ma it will be approximately 70 w . figure 19. cascading devices for increased output voltage 1 2 3 4 8 7 6 5 ICL7662 v+ 1 1 2 3 4 8 7 6 5 ICL7662 n 10 m f + - 10 m f - + v out - + 10 m f 10 m f - + 1 2 3 4 8 7 6 5 + - 10 m f ICL7662 v out v + + - 10 m f v + cmos gate 1k w figure 20. external clocking 1 2 3 4 8 7 6 5 + - ICL7662 v out v + + - c 2 c 1 c osc figure 21. lowering oscillator frequency 1 2 3 4 8 7 6 5 ICL7662 v+ d 2 c 1 c 2 v out = (2v+) - (2v f ) + - + - d 1 note: d 1 and d 2 can be any suitable diode. figure 22. positive voltage doubler ICL7662
3-54 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?cation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site http://www.intersil.com combined negative voltage conversion and posi- tive supply doubling figure 23 combines the functions shown in figure 16 and figure 22 to provide negative voltage conversion and positive voltage doubling simultaneously. this approach would be, for example, suitable for generating +9v and -5v from an existing +5v supply. in this instance capacitors c 1 and c 3 perform the pump and reservoir functions respectively for the generation of the negative voltage, while capacitors c 2 and c 4 are pump and reservoir respectively for the doubled positive voltage. there is a penalty in this con?guration which combines both functions, however, in that the source impedances of the generated supplies will be somewhat higher due to the ?nite impedance of the common charge pump driver at pin 2 of the device. voltage splitting the bidirectional characteristics can also be used to split a higher supply in half, as shown in figure 24. the combined load will be evenly shared between the two sides and, a high value resistor to the lv pin ensures start-up. because the switches share the load in parallel, the output impedance is much lower than in the standard circuits, and higher currents can be drawn from the device. by using this circuit, and then the circuit of figure 19, +30v can be converted (via +15v, and -15v) to a nominal -30v, although with rather high series output resistance (~250 w ). regulated negative voltage supply in some cases, the output impedance of the ICL7662 can be a problem, particularly if the load current varies substantially. the circuit of figure 25 can be used to overcome this by controlling the input voltage, via an icl7611 low-power cmos op amp, in such a way as to maintain a nearly constant output voltage. direct feedback is inadvisable, since the ICL7662s output does not respond instantaneously to a change in input, but only after the switching delay. the circuit shown supplies enough delay to accommodate the ICL7662, while maintaining adequate feedback. an increase in pump and storage capacitors is desirable, and the values shown provides an output impedance of less than 5 w to a load of 10ma. other applications further information on the operation and use of the ICL7662 may be found in an051 principles and applications of the icl7660 cmos voltage converter. 1 2 3 4 8 7 6 5 ICL7662 v+ d 1 d 2 c 4 v out = (2v+) - (v fd1 ) - (v fd2 ) + - c 2 + - c 3 + - v out = - (nv in - v fdx ) c 1 + - figure 23. combined negative converter and positive doubler 1 2 3 4 8 7 6 5 + - + - 50 m f 50 m f + - 50 m f r l1 v out = v+ - v- 2 ICL7662 v+ v- r l2 figure 24. splitting a supply in half 1 2 3 4 8 7 6 5 + - 100 m f ICL7662 100 m f v out + - 10 m f icl7611 + - 100 w 50k +8v 100k 50k icl8069 56k +8v 800k 250k voltage adjust + - figure 25. regulating the output voltage ICL7662
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